Field of the Disclosure
The present disclosure relates generally to processors and in particular relates to graphics context scheduling at a processor.
Description of the Related Art
To enhance processing efficiency, a processor sometimes employs a dedicated graphics pipeline to generate data for display at a display device. By employing a dedicated graphics pipeline, the processor removes the tasks of display data generation and management from its central processing units, allowing those units to execute operations related to system management and execution of user initiated applications. Based on these operations, the processor generates different graphics contexts, wherein each graphics context represents the instructions and state data to be used by the graphics pipeline in order to display one or more objects associated with the graphics context.
During execution at the graphics pipeline, a graphics context may generate a request, referred to as a flip request, to change a frame buffer being displayed. In some situations, execution of a command to change the contents of the buffer must be delayed until the display hardware is ready to execute the request. For example, a frame buffer targeted by the flip request may be in the process of being used when the command to change the contents of the frame buffer is made so that immediate execution of the command could result in tearing or other display errors. To prevent these errors, execution of operations at the graphics pipeline is stalled until the frame buffer is available to execute the command, but such delays can negatively impact processing efficiency.